Join our cutting-edge start-up adventure!

Who are we?

Join the Revolution in GNSS and IoT Connectivity

At Qualinx, we’re not just building chips, we’re engineering the future fabric of the connected world. As a pioneering semiconductor scale-up, we’re transforming how devices connect, communicate, and operate through our ground-breaking Digital RF technology. Our mission goes beyond ultra-low power GNSS: we’re redefining what’s possible in adaptive, scalable, and intelligent connectivity for the Internet of Things.

Born from deep-tech innovation at TU Delft, our team of visionary engineers and bold thinkers is tackling the toughest challenges in GNSS and IoT, starting with power consumption and expanding into dynamic, context-aware solutions that adapt to any environment or use case. We’ve already achieved what many thought impossible: the world’s most advanced GNSS chipset. But that’s just the beginning.

At Qualinx, we believe that the future of connectivity lies in precision, efficiency, and adaptability. Our ambition is to become the invisible thread that seamlessly interconnects billions of devices: powering a smarter, more responsive world.

What Sets Us Apart

Joining Qualinx is about becoming part of a culture that’s as ambitious as it is authentic. We hold ourselves to high standards, thrive on solving the unexpected, and push boundaries together. But we also know how to enjoy the ride. Our culture is a unique blend of curiosity, team spirit, and a touch of unconventional charm. It’s fast-paced, fun, and grounded in a sober sense of purpose and perspective. Whether we’re deep in design reviews or sharing laughs over lunch, we’re building something meaningful together. At Qualinx, you’re not just contributing to a ground-breaking technology, you’re helping shape a team that’s redefining what it means to work in deep tech.

Job Description

As a Team Lead Digital ASIC Verification Engineer, you'll play a role in shaping the future of our cutting-edge technology. You will be responsible for the verification of our digital IP blocks and the simulation of Chip level post-layout within our upcoming SoCs. You will contribute to the circuit design for our next-generation products.

• You are responsible for ASIC verification, System Verilog, and UVM.

• You will be responsible for the simulation and verification of digital block implementation in RTL for various functions, including control state machine digital processing (DSP), and multiple clock domain interface management.

• During your work at Qualinx you will be responsible for the post-layout simulation of complex mixed-signal SoC.

• As a Digital ASIC Verification engineer you will develop test benches and test cases for block-level functional verification.

• You will work with our backend and implementation teams to address synthesis, timing, DFT issues for the ASIC implementation.

• You understand all design integration activities like Lint, CDC, Synthesis & ECO.

• You will define the verification and test plan, run regressions, reproduce, and debug functional and performance bugs.

• You are responsible for the verification of various IPs/Sub IPs integrated to the top level SoC.

• Lastly: you will have an understanding of the design synthesis and fix timing issues for the Physical Design team.

Requirements

At Qualinx, we seek a result-driven Team Lead Digital Verification who thrives in an environment where proactive, can-do attitudes are celebrated. Bring your passion and expertise and join us on this exciting venture. The ideal candidate should have:

• Bachelor's degree or higher in Electrical Engineering

• 10+ years of experience as an ASIC Verification Engineer.

• A couple of years of experience as a team lead.

• Proficiency with EDA tools and design languages including Verilog.

• Experience with standard EDA tools like Candence and Mentor.

• You have experience in designing complex mixed-signal products containing analog building blocks and microcontrollers.

• You have worked with RTL and ultra-low-power designs before. Good knowledge of digital design flow from architecture design to sign-off

• You understand synthesis, static timing analysis, and netlist verifications

• You have some previous experience in digital backend flow for Floor Planning and Place & Route (PNR)

• You understand digital DFT/ECO flow

• You have strong programming and scripting skills: MATLAB, C/C++, Tcl

• Experience in setting up Power Distribution architecture, power intent specification and validation methodology.

• Strong knowledge of clock domain crossing (CDC) techniques.

• Understanding of digital design flow including RTL simulation, logic synthesis, timing constraints, timing closure, STA, back annotation of parasitics, gate level simulation

• Understanding of ASIC test methodology such as scan insertion, memory BIST and test pattern generation

• Strong analytical, problem-solving skills.

What's in it for you?

At Qualinx, we believe that great work starts with a great environment, pioneering technology and a fun dynamic market to address. Here’s what you can expect when you join our team:

• Ownership and Impact: We offer employee equity, giving you the opportunity to share in the success you help create.

• Well-being Matters: Your physical and mental health are important to us. We provide access to wellness resources, including company discounts and a free mental healthcare platform.

• Global Talent, Local Support: If you're relocating from abroad, we provide full support throughout the visa process to ensure a smooth transition.

• Future-Focused Benefits: We contribute to your pension savings to help you plan ahead with confidence.

• Inspiring Workspace: Work from a modern and vibrant, well-equipped office designed to help you do your best work.

• Scale-up Team Spirit: We celebrate our wins together with fun quarterly events—think great food, games, and unforgettable experiences.